In the electronics industry, integrated circuit device manufacturers design and produce commodity parts that are capable of operating in a variety of electronic systems that have different electronic specifications. For example, dynamic random access memory (DRAM) devices are designed for use in electronic systems with a wide range of power supply voltage. To keep pace with changes in system specifications, device manufacturers face the difficult task of designing new parts that operate over a wider range of conditions.
A DRAM is comprised of an array of individual memory cells. Typically, each memory cell comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and columns, and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell must be selected, or addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the column address. For a read operation the selected word line activates the access transistors for a given row address, and data is latched to the digit line pairs.
Conventional DRAMs use memory cells fabricated as capacitors in an integrated circuit to store data where a logical "1" is stored as a charge on the capacitor and the capacitor is discharged for a logical "0". The pairs of digit lines are typically fabricated as metal lines on the integrated circuit and connected to the memory cells for transmitting data stored in the memory cells. Sense amplifiers are utilized to sense small differentials on the digit lines and drive the digit lines to full power supply rails for either reading or writing the memory cells.
Typically, a sense amplifier includes a pair of n-channel transistors having a cross-coupled gate and drain configuration. Due to the positive feedback of this configuration, the sense amplifier senses slight changes in the voltages on the digit and digit complement lines and produces full logic values on the digit lines based on the slight voltage differential. The source of each transistor is coupled to a pull-down circuit, which, in operation drives the source of the transistors to ground thus allowing the sense amplifier to amplify the small changes in voltage on the digit and digit complement lines.
Conventionally, the pull-down circuit of an n-channel sense amplifier comprises an n-channel MOS transistor. Unfortunately, conventional pull-down circuits do not function properly over the wider range of power supply voltages demanded by newer systems. At low supply voltages, the current in a typical pull-down circuit is not sufficient to allow the sense amplifier to settle quick enough to produce an accurate reading at the digit lines. Further, at high power supply voltages, the pull-down circuit draws too much current and drives the common source and the drains of both transistors to ground before the digit lines can reach the proper voltages.
Therefore, since current generation DRAMs rely on the analog sense amplifiers to correctly sense a small amount of stored charge in a memory cell and then amplify this charge to full digit-line voltages, the sense amplifiers are difficult to operate across a large voltage range for the power supply voltages. To aid in the operation of the sense amplifier, a current impulse that discharges a sense amplifier's common node must be carefully controlled with the pull-down circuit. If the current pulse is too small, the sense amplifier is not able to properly sense all digits in the given time period. If the current pulse is too large, the sense amplifier is essentially too strong and can corrupt data due to excessive noise and coupling mechanisms.
Therefore, for the reasons stated above, and for other reasons presented in greater detail in the Description of the Preferred Embodiments section of the present specification, there is a need in the art for a memory-integrated circuit having sense amplifier circuitry which functions properly over a wide range of power supply voltages.